Virtualization and high-performance computing (HPC) dominated the conversations at Street Grid and Linux on Wall Street (LoWS) in April. While there is no doubt virtualization is driving up utilization of compute capacity, the industry expressed concerns over performance—sentiments which were again reflected at our London roundtable.

Anne Gregory Financial Services Solutions Marketing Intel

During the LoWS keynote presentation “Optimizing Linux and Open Source Applications for Multi-Core Architectures,” we heard: “As you put more virtual machines on these physical machines, you need more memory—you can share the CPU between a bunch of applications, but you can’t share the machine memory.”

Fortunately, Intel’s multi-core, multi-socket roadmap gives plenty of headroom for HPC engineering, with our 24-month new release schedule set to raise the performance bar continually. Coupled with our move to 45nm technology, power thermal characteristics are now well under control, helping to manage the energy footprint of datacenters.

Another engineering demand we’ve been hearing is to ensure that both firms and vendor products are set up for multi-core and multi-threading. At Street Grid, Barry Childe of Barclays Capital challenged Intel to deliver out-of-the box virtualization.

“I would like to see Intel offer me virtualization as an appliance, instead of my having to carry the cost of ownership of another layer between my application software, my OS, and the chip itself. I’d like to see that problem go away from me. I don’t want to have all these third-party platforms in the middle of everything—you know it’s bad enough making a set of hardware work as an appliance.”

You can’t argue with the logic, so let’s see if it’s possible! Certainly, as more and more focus is being applied under the infrastructure hood, it’s only a matter of time before today’s niche accelerator and utilization tools become bundled solutions rather than the engineering components they are today.

Acceleration in some quarters is at fever point, and the adventurous cannot resist the foray into FPGA and similar machine-based engineering. While the possible increase in speed is often colossal, the challenge becomes how to make this mainstream and leverage across the massive inventory of existing and emerging code. This is where Intel’s Geneseo strategy comes to the rescue.

Working alongside toolset vendors like FPGA computing specialist Nallatech, we are providing a unique software layer called the Intel® QuickAssist Technology Accelerator Abstraction Layer (AAL) and validated hardware building blocks for the bus protocol FSB Register Transfer Logic (RTL). Why should developers spend so much time developing and debugging the bus protocol and waste all that bandwidth creating their own hardware and software interfaces for accelerator integration? With this solution, end-users can accelerate the performance of computationally intensive algorithms significantly while, most importantly, staying aligned to mainstream technologies.

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Filed under: Issue 2 - Summer 07