In 2006, Intel’s core microprocessor architecture made its debut with dual-core and quad-core variants. This year, these technologies are being augmented with multi-core and 45 Nanometer advances. The superior performance improvements offered by these parallel chip technologies have placed Intel firmly in front of the trading technology arms race—where microseconds really do count.

Rob Wenham Financial Services Sector Business Manager Intel

Propelling this arms race is the quest for low latency across the entire trade life-cycle. While many accelerators and tuning techniques are now available to achieve lowest latency, many financial services IT teams lack the multi-threading skills, time, or access to innovation to tune and upgrade today’s operational infrastructures adequately. To help meet the challenge of maximizing performance, Intel has set up the Low Latency Lab program.

Launched in April this year, the Intel Low Latency Lab is a facility that gives financial institutions unique access to the very latest high-performance technologies from Intel and its complementary partners in the trading arena.

To unlock the Lab’s potential, practical targeting and understanding of the most relevant infrastructure elements has to be conducted. Normally, this is undertaken by workshop under strict NDA conditions by the Intel team and, if required, pre-qualified partner technologists. The Low Latency lab is unique in its low-cost access to a choice of technologies and scenarios. Already, it has attracted the interest of several tier one banks and vendor solution combinations for performance benchmarking.

A classic understanding and discovery session feeds the construction of a proposal to identify the elements for lab activity that enable performance gains. This phase creates a detailed architectural analysis, identifies areas of concern, and provides a roadmap for repairing, improving, or replacing barriers to a low latency infrastructure.

Lab engineers follow this optimization roadmap using a wide choice of hardware, connectivity options, and suitable ISV components.

“We have seen a lot of interest in the breadth we are offering to address latency and impart Intel’s philosophy of standards in both technology and measurement—absent to date in the trading space,” says John Barr, Lead Solutions Engineer at Intel Financial Services. “The opportunity to test different combinations of technology and operational scenarios delivers considerable value to a client’s evaluation of solutions to meet latency challenges—reducing development costs and managing project risk at the same time.”

Adding to the lab experience is the technical and consultancy services of the Intel Solution Services team. Applying their project disciplines establishes a clear path to technology and data-center strategies.

The work of the Low Latency Lab is designed with the wider picture in mind. Growth plans promise more services, including benchmarking on new platforms, early access to solutions for XML, FPGA, and other acceleration technologies, virtualization testing, and thin client solutions.

Within the automated trading landscape, the search for competitive advantage through increased performance remains constant. New regulations, technologies, and interpretations of their optimum combination are continually entering the market. As X86 technology becomes ubiquitous across trading systems, competitive advantage will come from optimizing the standard elements. This is where Intel Architecture can deliver a Formula 1 edge.

The Low Latency Lab acts as a testing facility, technology pit stop, and trading solution factory. Using Intel’s suite of software tools, including Intel® VTune™ Performance Analyzer, threading equipment, libraries, and compilers, the lab radically improves performance on X86 architecture so financial institutions can achieve pole position.

If you are interested in using the Intel Low Latency Lab facility, please contact: fastertrading@intelfasterfs.com

Work closely with the best technologists from across the financial services industry to design and test optimal performance infrastructures.

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Filed under: Issue 2 - Summer 07